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Wafer and Die Thinning Technology

Technical Description:

The NSA is engaged in the development of many high value enabling technologies in support of government requirements requiring dense microelectronics. Key enabling technologies have been developed for use in several projects which can provide thin circuitry in wafer or die form in the thickness range of 5 to 50 microns. A variety of thinning technologies have been put into practice and can be tailored to 25 microns and circuitry has been thinned to 15 microns. Thinning technology is scalable to the limit of operation of the device which can be as small as about 3 microns for SOI circuitry. Die level thinning for medium volume applications is currently under development. All methods for thinning allow for post thinning functional test to identify known good die. Mechanical and electrical tests of full wafers thinned to these thicknesses have shown that circuitry may be flexed repeatedly to small radii of curvature with high yield and no significant change in transistor parametrics. Thinned circuit manipulation technology has also been developed. Several U.S. Patent applications have been filed.

Commercial Application:

nned silicon circuitry for:
  • Electro-Optic Devices
  • Thin Multi-Chip Modules
  • Substrate-less Multi-Chip Modules
  • Thin, Conformal Multi-Chip Modules
  • Satellite/RPV Microelectronics
  • Smart Card Electronics
  • Light Weight Terra Bit Memories

Released: 1996

Reference Number: Mou-2

If you are interested in exploring this technology further, please call 443-445-7159 or express your interest in writing to the:

National Security Agency
NSA Technology Transfer Program
9800 Savage Road, Suite 6541
Fort George G. Meade, Maryland 20755-6541

 

Date Posted: Jan 15, 2009 | Last Modified: Jan 15, 2009 | Last Reviewed: Jan 15 2009

 
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