Wafer Level Coating Designed to Protect Integrated Circuits From Reverse Engineering
Technical Description:The proliferation of integrated circuits in applications ranging from toys to computers, cable television and bank cards has led to a critical requirement for protection of proprietary technology and intellectual property located on the integrated circuit. Information related to circuit design, as well as stored in the integrated circuit, may be recovered by reverse engineering of the circuitry. A novel wafer level coating has been developed to protect integrated circuits from reverse engineering. The wafer level protective coating consists of a non-etchable opaque coating which is screen printed over the active circuitry at the wafer level. This screen printing process is followed by the addition of a spin-on planarization layer and a PECVD deposited abrasion and etch resistant coating. Several formulations of the wafer level coating have been developed including a formulation which has been developed for commercial applications. Advantages of the wafer level coating process include: rapid automated processing, thin coating compatible with all package designs, known good die, economical process, elimination of thermal processing following the wire bonding required for package level coatings, and coating of the devices earlier in packaging process. The opaque coating is U.S. Patent No. 5,258,334. This technology will be licensed for use to protect proprietary commercial technology and intellectual properties.
Reference Number: Lan-1
If you are interested in exploring this technology further, please call 443-445-7159 or express your interest in writing to the:
National Security Agency
Date Posted: Jan 15, 2009 | Last Modified: Jan 15, 2009 | Last Reviewed: Jan 15 2009