Recovering an Integrated Circuits (ICs) Gate-Level Netlist from a Transistor-Level Netlist Using the EXTRACT Algorithm
Technical Descrition:The EXTRACT algorithm is broken into two parts. First, we create a "Relational Signature" for every cell in a standard cell library (currently we are focusing on the CMOS technology). This relational signature represents information within identities of the functionality parameters of the cell. Once these relational signatures are computed, we use them in the next step to recover the identities of the unknown "candidate" cells and produce the gate level netlist for the IC. These candidate cells are created by partitioning a flat transistor level netlist and dividing it into a list of unknown candidate cells. EXTRACT will then process each candidate cell, one at a time, and use functional information captured in the relational signature to identify the unknown candidate cell. Our approach is not subjective in nature to the style/design preference of the designer of the IC (in any cases, the designer and his IC standard cell library are unknown). This is the main feature where our algorithm surpasses the current leading algorithm, REDUCE, on this problem. Submitted for patent review.
Commercial Application:Our EXTRACT algorithm will offer a more efficient, cost effective way to recover a gate level netlist from a transistor level netlist.
Patent Status:Issued: United States Patent Number 6,190,433 (Updated)
Reference Number: Netlist
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Date Posted: Jan 15, 2009 | Last Modified: Jan 15, 2009 | Last Reviewed: Jan 15 2009