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Native Ooxide Formation Technique for Group III-V Semiconductor Device Fabrication that Enhances the Oxidation Rate


Selective oxide formation for Group III-V semiconductor device fabrication that enhances the oxidation rate.

Technical Challenge:

Unlike the ease with which silicon can be controllably oxidized to create thin-film oxide layers during silicon-based electronic device fabrication, thin-film oxide formation during the fabrication of electronic and optoelectronic devices based on the technologically important Group III-V semiconductor materials presents several challenges to device designers and fabricators. Mitigating these challenges is of particular interest to designers of devices that are lattice matched to indium phosphide, important for their optical communications and high-speed electronics applications.

Thin-film oxide layers situated amid or upon the multiple, single-crystal, thin-film semiconductor layers that compose electronic and optoelectronic devices are useful for their electrical insulating and low refractive index properties. The oxide layers are, in some cases, essential for device operation (e.g., the gate oxide in MOSFETs) and can, in other cases, enhance device performance (e.g., low refractive index material for the fabrication of DBR mirrors, and current and optical guiding apertures for lasers).

By and large, the preferred method of creating these thin-film oxide layers in device structures is by a selective oxidation process, rather than by thin-film oxide deposition. Unlike thin-film oxide deposition techniques (CVD, sputtering, etc.), selective oxidation can result in excellent oxide-III-V semiconductor interfaces, and can produce "buried" oxide layers without the need for supplementary epitaxial growth ("regrowth"). In general, the selective oxidation technique is a "wet" thermal process involving time-limited exposure of a device structure to temperatures around 500 degrees Celsius in a oxidizing ambient (e.g., water vapor). During this process, specific thin-film semiconductor layers, having been deposited among the other thin-film semiconductor layers during device epitaxial growth (MBE, MOCVD, etc.), undergo hydrolyzation oxidation. This transformation begins at the edges of these layers, exposed at the sidewalls of the device, and progresses laterally toward the center of the structure, leaving behind stable oxide layers amid the semiconductor layers of the structure. The other layers of the device are essentially unaffected by this process.

But application of the selective oxidation technique to the fabrication of devices based on Group III-V semiconductor materials is complicated by the limited selection of materials that (1) can be oxidized using a well-controlled process that is compatible with established device processing procedures and will not alter the other single-crystal thin-film semiconductor layers that compose device structures, and (2) are crystal lattice matched to commercially available Group III-V semiconductor substrates (GaAs, InP, etc.). Based on current knowledge, the only Group III-V semiconductor materials that can be readily and controllably oxidized using a selective oxidation process are those materials having high aluminum content. Examples of these materials include the binary AlAs, and the ternaries AlxGa(1-x)As, and AlxIn(1-x)As, where x, the aluminum mole fraction, is much greater that 0.5. (Unlike the room temperature, air-formed oxides of high aluminum content Group III-V semiconductor materials that eventually turn into powder, the wet thermal oxides of these materials are structurally sound and stable.)

The challenge, then, for device designers in search of a material for selective oxidation purposes in Group III-V semiconductor-based device structures has been to find a high aluminum content material that is lattice matched to the substrate on which the devices are based. (Lattice-matching between the multiple semiconductor layers that compose a device structure and the substrate on which they are deposited is necessary to ensure that the elastic strain energy in the layers is less than the misfit dislocation formation energy. Dislocations can degrade device performance.)

Device structures lattice matched to GaAs present little challenge to device designers in this regard. Given that the AlAs and GaAs lattice parameters are matched within 0.1 percent, AlAs or high aluminum-content AlxGa(1-x)As layers situated among the other semiconductor layers of a GaAs-based device introduce little elastic strain energy into the structure and can be selectively oxidized using a wet thermal selective oxidation process. Selective oxidation of AlAs and high aluminum content AlxGa(1-x)As layers in device structures lattice matched to GaAs has been successfully employed in the fabrication of various electronic and optoelectronic devices.

But most commercially available semiconductor substrates (and the device structures grown lattice-matched thereon) are not lattice matched to a high aluminum content Group III-V semiconductor material, creating a major hurdle for device designers. An important example is device structures lattice matched to InP, important for their optical communication and high-speed electronics applications.

Two aluminum-bearing Group III-V semiconductor materials are lattice matched to InP, namely the ternaries AlxIn(1-x)As and AlAsxSb(1-x), where x is around 0.48 and 0.50, respectively. But in the case of AlxIn(1-x)As, the aluminum content is relatively low, leading to a low oxidation rate (approximately 1 micron per hour at 500 degrees Celsius). Consequently, during the wet thermal oxidation process, an InP-based device structure that includes a layer of this ternary for selective oxidation will be subjected to an elevated temperature for an excessive period, leading to degradation of the device. Increasing the aluminum content of the ternary will increase its oxidation rate but will also increase the lattice mismatch between the ternary and InP, leading to a rise in the elastic strain energy that could result in the formation of device-degrading misfit dislocations.

Alternatively, AlAsxSb(1-x) is lattice matched to InP for x equal to approximately 0.50, as stated above. But during the oxidation process, As and Sb separate and form conductive interfacial layers at the oxide-semiconductor interface, resulting in lattice strain that may lead to reduced device reliability.

Apparently, no suitable material is available that can be selectively oxidized in an InP-based device structure without compromising device integrity: high aluminum content, Group III-V semiconductor materials are not lattice matched to InP, and aluminum-bearing materials that are lattice matched to InP oxidize too slowly or produce lattice strain when they are oxidized, adversely affecting device performance. A similar quandary afflicts device structures based on other commercially available substrate materials.


The technology is a rapid, well-controlled selective oxidation technique for forming a high quality native oxide upon or amid a Group III-V semiconductor structure. Oxidation is achieved using processes that are compatible with established device processing methods and will not degrade the structure in which the oxide is formed. The native oxide thus formed has an excellent interface with the adjacent semiconductor layers, is a good electrical insulator, has a low refractive index and is structurally sound and stable. Being a selective oxidation technique, "buried" oxide layer formation is possible without the need for "regrowth."

In general, the technique is applicable to the fabrication of electronic and optoelectronic devices lattice matched to substrates that are not lattice matched to a high aluminum content Group III-V semiconductor material. In particular, the technique is applicable to the fabrication of devices that are lattice matched to indium phosphide substrates.

Device applications of the technique include, but are not limited to:

  • low refractive index material for the fabrication of distributed Bragg reflector mirrors in VCSELs
  • oxide-defined aperture, formed without regrowth, to minimize lateral current leakage and to reduce the effective gain volume with minimal optical scattering losses in stripe-geometry lasers and VCSELs
  • gate oxide for MOSFETs

Demonstration Capability:

Although Dr. Johnson has left NSA, the Laboratory for Physical Sciences retains the equipment and technical expertise to demonstrate this technology. One paper was published that demonstrates the technique and related improvements in laser device performance:
B. Koley, F.G. Johnson, O. King, S.S. Saini, and M. Dagenais, "A method of highly efficient hydrolyzation oxidation of III-V semiconductor lattice matched to indium phosphide," Applied Physics Letters 75, p. 1264 (1999).

Potential Commercial Application(s):

Compound semiconductor electronic and optoelectronic device manufacturing.

Patent Status:

Issued - United States Patent Number 6,531,414

If you are interested in exploring this technology further, please express your interest in writing to the:

National Security Agency
NSA Technology Transfer Program
9800 Savage Road, Suite 6541
Fort George G. Meade, Maryland 20755-6541


Date Posted: Jan 15, 2009 | Last Modified: Jan 15, 2009 | Last Reviewed: Jan 15 2009