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Method of Bumping a Thin Wafer


Low profile SiP

Technical Challenge:

Portable electronic devices such as PDAs are pushing the limits of electronic miniaturization. The drive to get more performance with limited physical space requires a continuous improvement in densifying electronic assemblies. Even the thickness of the integrated circuits is being reduced. At the same time, high yields and manufacturability processes are needed to keep costs down.


This invention addresses fabricating very thin wafers with solder bumps for advanced chip-scale packaging that eliminates technical problems such as handling and alignment associated with flip-chip attachment. By using this method, extremely thin chip scale packages can be manufactured reliably, with high yield, and using standard equipment sets.

Demonstration Capability:

Samples available for evaluation. Run sheets for the method are available. Process demonstrations are also available.

Potential Commercial Application(s):

Portable electronic devices, high density and high-speed electronic modules, and ultra-miniature chip assemblies.

Patent Status:

Issued: United States Patent Number 7,232,740 (Updated).

Reference Number: 1351

If you are interested in exploring this technology further, please call express your interest in writing to the:

National Security Agency
NSA Technology Transfer Program
9800 Savage Road, Suite 6541
Fort George G. Meade, Maryland 20755-6541


Date Posted: Jan 15, 2009 | Last Modified: Jan 15, 2009 | Last Reviewed: Jan 15 2009